The instructions of this group are concerned with simple shifts. Facilities are provided for shifting single- and double-length quantities.
In all these instructions the quantity to be shifted is that in register X if single-length or that in registers X and X+l if double-length. If the instruction is of 3-address type the result is written into Z (or Z and Z+1) while in 2-address type the result is written into X (or X and X+1).
The number of places by which the quantity is shifted (the 'shift number') is Y, which may be a number written in the instruction or may be obtained by replacement; whichever alternative is used, the shift number may also be modified using internal and/or external modification. If Y is written in the instruction as a negative integer it is treated as such, i.e. although it is stored as 15 bits, the sign bit is repeated in the control circuits when the instruction comes to be obeyed. (For fuller details of formation of shift-number, see later.)
Generally a shift may be 'up' or 'down'. (Alternative terms are 'left' and 'right' respectively). If a quantity is shifted up, each bit is moved through Y digit-positions towards the more-significant end, while if it is shifted down, each bit is moved through Y digit-positions towards the less-significant end. In general, such movement results in some digit-positions becoming vacant and in some bits being moved off the end of the word. In double-length shifts some bits are transferred from one word to the other. The action in such cases depends on whether the shift is logical or arithmetical.
(a) Logical, single-length. Those bits which are moved off the end of the word are lost; those digit positions vacated at the other end of the word are filled with zeros. OVR cannot be set.
(b) Logical, double-length. Action at the ends of the d.l. quantity is as stated under (a) above. Those bits which pass from one word to the other do so without special treatment; the effect is as though the two registers containing the d.l. quantity had been temporarily joined to form a single 96-bit register. OVR cannot be set.
(c) Arithmetical, single-length.
i) Shift up. Digit positions vacated at the l.s. end are filled with zeros. OVR is set if the result exceeds capacity (i.e. if significant 1-bits are shifted off the m.s. end, or if the sign apparently changes).
ii) Shift down. The result is rounded; if the last bit shifted off the l.s. end is a 1, a 1-bit is added to the least-significant end after the shift before the result is written away. The sign-bit is propagated; digit-positions vacated at the m.s. end are filled with copies of the sign-bit. These special actions lead to the result being correctly signed and rounded. OVR cannot be set by a shift down.
(d) Arithmetical, double-length. The action at the ends of the d.l. number is as stated in (c) above. In addition a double-length arithmetical shift includes a 'partial-justify' operation. If the l.s. word of the pair is negative (i.e its sign-bit is a 1) the d.l. quantity is adjusted so that the l.s. word is non-negative (its sign-bit is a 0), the m.s. word being adjusted so that the value of the double-length quantity is unchanged. Thereafter the sign-bit of the l.s. word is excluded from the shifting process. Those bits which pass from one word to the other effectively 'skip over' D0 of the l.s. word. For example, if a d.l. quantity is shifted arithmetically up by one place, then D1 of the l.s. word of the original quantity is shifted to become D47 of the m.s. word of the result, passing over D0 of the l.s. word. OVR cannot be set by a shift down but will be set if the result of an upward shift exceeds capacity. The 'partial justify' is still performed (and may set OVR) if Y=0.
In all instructions of this group, the shift number Y is treated as signed. Thus if Y is negative, a function-number which nominally produces a shift up will in fact produce a shift down and vice-versa.
The shift-number is formed as described below.
If Y is not replaced, the 15-bit representation of Y is extended upwards
to 24 bits
by repeating the m.s. bit of Y.
If Y is replaced, it is replaced
by ym as usual. (Y may
have been pre-modified (116-instruction)
before the replacement).
If Y is internally modified (2-address modified instruction), zm is added to the 24-bit result of (i) or (ii).
If Y is externally modified (116- or 117-instruction) and:-
a) the Y-address in the pre-modify instruction is not replaced: the 15-bit Y, right-justified , from the pre-modify instruction is added to the 24-bit result of (i), (ii) or (iii).
b) the Y-address in the pre-modify instruction is replaced: the 24-bit modifier in the replaced Y-address of the pre-modify instruction is added to result of (i), (ii) or (iii).
Thus a 24-bit effective shift-number is obtained. If the m.s. bit of this is a 1, the shift-number is negated and the shift takes place in the opposite direction to the nominal sense for the function. Of the 24-bit shift-number (after the negation, if any) the logical 'or' operation is performed between the eighth bit from the l.s. end and each of the l6 m.s. bits, producing an 8-bit shift-number; in effect, if any of the 17 m.s. bits is a 1, the eighth bit is made a 1. Hence if the 24-bit shift number exceeds, in modulus, 255, the actual number of places shifted is 128+ the l.s. bits of the shift number. In such a case the result of a group 5 instruction is always zero but OVR may be set by an arithmetical shift up. A consequence of this treatment of the shift number is that a shift can never take more than one millisecond.
Function number 50 [0101 000]
3-address: z' = x.2Y 2-address: x' = x.2Y
the number x by 2Y, writing the result into Z or X.
The result is correctly signed and, if Y is negative, rounded.
OVR is set if the result is out of range.
Function number 51 [0101 001]
3-address: z' = x.2-Y 2-address: x' = x.2-Y
x by 2Y writing the result into Z or X.
The result is correctly signed and rounded. OVR is set if the result is out of range which can happen
only if Y is negative.
Function number 52 [0101 010]
3-address: z' =
xL shifted logically up Y places.
2-address: x' = xL shifted logically up Y places.
OVR cannot be set.
Function number 53 [0101 011]
3-address: z' =
xL shifted logically down Y places.
2-address: x' = xL shifted logically down Y places.
OVR cannot be set.
Function number 54 [0101 100]
3-address: z:' = x:.2Y 2-address: x:' = x:.2Y
Multiply the double-length number x: by 2Y, writing the result into Z and Z+1 or into X and X+1. The result is correctly signed and, if Y is negative, rounded. OVR is set if the result is out of range.
Note that the result is in standard form, i.e. with the l.s. word non-negative even if the original d.l. number is not in standard form. This means, for example, that if Y = 0 and x* < 0, the result will be such that z:' (or x:') = x: but z*' (or x*') ≠ x*. Thus if, say xI = 247k-j then, after a 54-instruction with Y = 0, zI' = k-1 and z*I' = 247-j giving
z:I' = 247(k-1) + (247-j)
= 247k - j
If, in a similar case, Y = 1 then the results would be zI'= 2k-1 and z*I' = 247-2j giving
= 247 (2k-1) + (247 - 2j)
= 2 (247k - j)
Function number 55 [0101 101]
3-address: z:' = x:.2-Y 2-address: x:' = x:.2-Y
Divide the double-length number x: by 2Y, writing the result into Z and Z+1 or into X and X+1 . The result is correctly signed and rounded. OVR is set if the result is out of range which can happen only if Y is negative. The result is left in standard form (see discussion under function-number 54 above). If the 'partial justify' sets OVR, the correct result is still obtained, i.e. after a shift down OVR will left clear.
Function number 56 [0101 110]
3-address: z:' = x:L shifted logically up Y places.
2-address: x:' = x:L shifted logically up Y places.
OVR cannot be set.
Note that a special use of a 56-instruction is typified by
56 A100 0 A7
which sets (A7)' = (A100) and (A8)' =
(A101), i.e. copies two consecutive words into two consecutive accumulators by a
single instruction, taking some 72 microsecs. as against 96 microsecs. for two
04-instructions. This use of a
56-instruction is permissible since there is no 'partial-justify' operation
when performing a logical shift.
Function number 57 [0101 111]
3-address: z:' = x:L shifted logically down Y places.
2-address: x:' = x:L shifted logically down Y places.
OVR cannot be set.
A 57-instruction may be used for a two-word copy as
discussed under function-number 56 above.
Another special use of a 57-instruction is to clear to zero two consecutive accumulators. This done by e.g.
57 A0 48 A7
which takes some 72 microsecs. (the last 48 places shifted take no time). Two 14-instructions take the same time but occupy one more register and a 143-instruction clearing two words takes about 80 microsecs.